Objective:
Upon completion of this lab, the student will have demonstrated the ability to:
? Use Quartus II software to program an Altera FPGA (DE0-CV educational board)
? Define an 8-bit register to store data using VHDL
? Define shifting behaviour to create a shift register using VHDL
? Define synchronous and asynchronous behaviour for devices using VHDL
Procedure:
In lab 4, you were asked to define a flip-flop to store a single bit of data using VHDL, which was then
used to create a 4-bit flip-flop in a schematic (BDF) file.
In this lab, you will define a multi-bit memory element (referred to as a register) using VHDL only. In
addition, you will extend the behaviour of your register so that it is capable of shifting data bitwise in
left or right, thus creating a universal shift register

Attachments:

Lab-6—Shift….pdf