For this assignment you are to design, simulate and verify the operation of a sequential logic circuit with unique behavior based on your Student Identity Number (SID). You may use either the LTspice CAD tool or National Instruments Multisim simulator in Part-1 to perform all the relevant simulations. Whereas in Part-2, you may use Symphony EDA Sonata (obtainable in http://www.symphonyeda.com/) You need to submit your documented work through the designated Blackboard submission portal as a single document by 23:59 on the day of the stated deadline. Document all your engineering work using this task sheet as a template. Name the document using this filename format:
201CDE.2020-04.CW2.YourName.YourSIDNumber
e.g.
Marks for each section and its sub-sections are stated in square brackets.
Enter the last seven digit of your student identification number (SID) in Table-A. The individual digit of your SID will serves in the design specifications that follow. All the seven digits will be treated as hexadecimal digits.
| Digit-A | Digit-B | Digit-C | Digit-D | Digit-E | Digit-F | Digit-G |
| 9 | 0 |
Table-A
| Part 1: | Sequential Logic Circuit Design and Simulation | [30] |
| Design a synchronous sequence detector that fulfills the following specifications:
1. Generates a logical 1 output when a correct 8-bit code sequence is detected sequentially. 2. The 8-bit code sequence to be detected is the binary equivalent of digits . e.g. SID example: 9857013 The last two digit (i.e. digits and of the SID) is “13”. The binary bit code sequence is thus , i.e. 000110002. The most significant bit (MSB) in the binary code is the first bit to be detected. The detection progresses until the least significant bit (LSB). 3. Use the Mealy machine model to implement the sequence detector, accepting overlapping sequences. 4. Use either or flip-flops as the state registers based on the list in Table-1.
Table-1 |
| Document all your design work by including the following non-exhaustive requirements: | ||
| · A clear Mealy model state diagram that illustrates the operation of the sequence detector. | [ 5 ] | |
| · A state transition table incorporating all the present and next states of the detector and its output. | [ 3 ] | |
| · The process to obtain the most optimized Boolean equations for all the excitation variables and the output variable. | [ 8 ] | |
| · A clear schematic diagram of the circuit design. | [ 5 ] | |
| · The simulation results that validate the circuit design. Assume that the set up time for each input bit meets the requirement of the synchronized clock signal. | [ 5 ] | |
| · Discussion on the simulated results. | [ 4 ] |
| Part 2: | VHDL Development and Simulation | [15] |
| a. | Write VHDL codes that describe the sequence detector behavior specified in Part-1.
Include comments the VHDL codes to effectively explain the processes of the codes. Provide clear “screen shots” of the VHDL codes in the report to ease the assessor’s marking. |
[ 5 ] |
| b. | Write VHDL test bench to thoroughly verify the VHDL codes in Part-2(a).
Take into considerations to verify the VHDL codes using various possible combination of input bit sequences. This means that you must verify the functionality of the VHDL codes to detect both the correct and incorrect bit sequence and verify if overlapping sequences are accurately captured. Include comments the VHDL test bench to effectively explain the processes of the testing. Provide clear “screen shots” of the VHDL codes in the report to ease the assessor’s marking. |
[ 5 ] |
| c | Based on the VHDL codes and test bench developed in Part-2(a) and Part-2(b) respectively, simulate the output waveform.
Include the output waveform in the report according to the test conducted. Discuss and interpret the simulated results. |
